# Project - Lightweight Arithmetic IP                  - Customizable computional cores for mobile multimedia appliances

"Lightweight arithmetic" is a family of customizable floating-point data formats that offers a wider range of speed/area/power /precision tradeoffs. The goal of this project is to create a library of parameterizable lightweight-arithmetic  IP  blocks, suitable for both media and silcon designers. We will deliver both robust, reusable arithmetic blocks as C++ and Verilog IP, and also quantify precisely how the broader flexibility offered by this IP translates into a better set of video-specific trade-offs among design complexity, required bit-width and perceived video/audio quality.

Multimedia algorithms are computationally intensive, richer in cosly arithmetic operations rather thatn simple random logic. These algorithms blocks are often on critical timing paths , and comsume large fractions of  the total chip energy budget.

Multimedia system designers prototype these algorithms as workstation programs using high-precision floating point operations, to understand how the algorithm behaves. Yet the ultimate hardware realization is rarely a floating point algorithm, which simply comsumes too much silicon area and power. The need to use only fixed-point operations often distorts the natural form of the algorithm, forces awkward design trade-offs, and even introduces artifacts percepttible to human ears and eyses.

So we propose a better solution:"Lightweight arithmetic IP" which is a rich set of real number formats, including reduced bit-width floating-point and fix point, and can bridge the gap between media designer and silicon designer.

Lightweigt Arithmetic IP

• Lightweight Arithmetic IP for algorithm designers:
We build a parameterized numerical C++ class ( Cmufix + Cmufloat ) and overload  all the operators ( + - * / , comparator, etc). Designers can eperiment to find exactly the right precision and range they need without affecting the overall structure of their code.

• Lightweight Arithmetic IP for silicon designers:
We provide a set of synthesizable Verilog arithmetic IP which can be used by silicon designers to simulate the same algorithms at behavioral digital logic level. Reductions in reqired bitwidth make it much easier to create floating point hardware ith standard ASIC sysnthesis norms.

Multimedia Demonstration Applications

• H.263 video codec

In H.263 video codec, the experiments prove that the floating point bitwidth can be cut down from 64 bits(double precision)  to 14 bits, with only less than 0.2 dB PSNR degradation, which is undetectable by human eyes.

• MP3 audio codec

In MP3 audio codec, the floating-point number can also be cut down to around 14 bits without causing perceptual noise in the music. The result also depends on the type of music. For rock music, the bitwidth can be even less than 14 bits.